Web Hosting Java, JSP, Tomcat 6, J2EE, Servlets, Struts, Jboss

The SMP Architecture The name SMP already describes

The SMP Architecture The name SMP already describes its characteristics: . It is a multiprocessor (MP). The system consists of multiple identical CPUs. . It is symmetric. All processors have an identical view of the system. They all have the same capabilities. For example, they have identical access to any location in memory as well as to any I/O device. . Everything else is single. It has a single memory system, a single copy of the operating system, a single run queue. Figure 7.3 depicts the architecture. Figure 7.3. The SMP architecture Unless your application code bends over backwards, threads have no affinity to any particular CPU. The same thread may execute on CPU_1 in one particular time-slice and CPU_2 on the next time-slice. Another idea shown in Figure 7.3 is that multiple threads really do execute simultaneously. While thread T1 executes on CPU_1, thread T2 may very well execute on CPU_2. Since the scheduling entity is a thread, there’s nothing to prevent threads T1 and T2 from belonging to the same process. In this case, it is very likely that they will access the same memory locations on a regular basis. That brings us to the next issue: There is only one bus connecting the processors to the memory system. The bus is the major bottleneck in SMP systems and the chief reason why 256-way SMP machines are not commonplace. Bus contention would bring them to a grinding halt. The solution to bus contention is large on-chip caches one per processor. A large on-chip cache would make bus trips infrequent, but would raise a new problem: What if two distinct caches both have a copy of a variable, x, and one of the processors updates its private copy? The other cache might have a stale, incorrect, value for x; we hate when that happens. This is the cache consistency Page 148
Note: If you are looking for high quality webhost to host and run your jsp application check Vision jsp hosting services